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Browsing by Author Ravikumar, C P

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Issue DateTitleAuthor(s)
1997Adaptive routing in k-ary n-cubes using incomplete diagnostic informationRavikumar, C P; Panda, C S
1995Deadlock-free wormhole routing algorithms for star graph topologyRavikumar, C P; Goel, A M
1996Efficient delay test generation for modular circuitsRavikumar, C P; Agrawal, N; Agarwal, P
1997Efficient implementation of multiple on-chip signature checkingAbdulla, M F; Ravikumar, C P; A Kumar
1996Estimation of power from module-level netlistsRavikumar, C P; Prasad, M R; Hora, L S
1997An Euler path based technique for deadlock-free multicastingAgrawal, N; Ravikumar, C P
1998Evaluating BIST architectures for low powerRavikumar, C P; Prasad, N S
1997Faster fault simulation through distributed computingRavikumar, C P; Jain, V; Dod, A
1996Fault-tolerant routing in multiply twisted cube topologyAgarwal, N; Ravikumar, C P
1999A functional-level testability measure for register-level circuits and its estimationRavikumar, C P; Saund, G S; Agrawal, N
1996A genetic algorithm for assembling optical computers using faulty optical arraysRavikumar, C P; Thomas, A R; Gupta, A
1996Genetic algorithms for scan path designRavikumar, C P; Rajarajan, N
1997A graph-theoretic approach for register file based synthesisRavikumar, C P; Aggarwal, R; Sharma, C
1995Heuristic and Neural Algorithms for Mapping Tasks to a Reconfigurable ArrayRavikumar, C P; Vedi, Naresh
1999Hierarchical delay fault simulationRavikumar, C P; Mittal, A
1995HISCOAP: a hierarchical testability analysis toolRavikumar, C P; Joshi, H
1998Hybrid testing schemes based on mutual and signature testingAbdulla, M F; Ravikumar, C P; A Kumar
1999Improving the diagnosability of digital circuitsRavikumar, C P; Sharma, M; Patney, R K
1992Interval partition with bounded overlapRavikumar, C P
1996A novel BIST architecture with built-in self checkAbdulla, M F; Ravikumar, C P; A Kumar
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