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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1645

Title: HISCOAP: a hierarchical testability analysis tool
Authors: Ravikumar, C P
Joshi, H
Keywords: hierarchical testability analysis
gate-level netlist
several benchmark circuits
Issue Date: 1995
Citation: VLSI Design, Proceedings of the 8th International Conference on, 272 - 277
Abstract: We describe a time and space efficient technique for evaluating the SCOAP testability measure of a circuit from its hierarchical description. Under the stuck at fault model, the SCOAP measure introduced by Goldstein is known to offer a good estimate of the controllability and observability of a given circuit. SCOAP works on a gate-level netlist, and can be expensive in terms of memory and computational resources when large circuits of VLSI complexity are involved. We show that this problem can be alleviated by taking advantage of a hierarchical representation of the circuit. We introduce the notion of SCOAP expression diagrams for functional modules, which can be precomputed and stored as part of the module database. The hierarchical testability analysis program, HISCOAP reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measures in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1645
Appears in Collections:Electrical Engineering

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