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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1688

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DC FieldValueLanguage
dc.contributor.authorJain, B N-
dc.contributor.authorMittal, R-
dc.contributor.authorPatney, R K-
dc.date.accessioned2006-06-23T11:08:07Z-
dc.date.available2006-06-23T11:08:07Z-
dc.date.issued1989-
dc.identifier.citationDistributed Computing Systems, 524 - 531en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1688-
dc.description.abstractAn augmented binary (AB) tree architecture is proposed with a view to providing fault tolerance. This architecture is an augmentation of an n-level full binary tree with n redundant nodes and 2 n+3n-6 redundant links. The AB tree can be configured into a full binary tree even when one node is faulty at each level. While functionally equivalent to the RAE-tree, the proposed AB tree has a regular topology, reduced number of maximum input-output channels per processor, and fewer wire crossovers when implemented using very large-scale integration layout. A reconfiguration algorithm, which constructs an n-level full binary tree from an n-level faulty AB tree, is given. A distributed fault diagnosis algorithm is given which runs concurrently on each nonfaulty processor, enabling each nonfaulty processor to identify all faulty processorsen
dc.format.extent94119 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectaugmented binary (AB)en
dc.subjectfault toleranceen
dc.subjectn-level full binary treeen
dc.subjectredundant nodesen
dc.subjectfewer wire crossoversen
dc.subjectdiagnosis algorithmen
dc.titleFault-tolerant analysis and algorithms for a proposed augmented binary tree architectureen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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