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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1688
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| DC Field | Value | Language |
|---|
| contributor.author | Jain, B N | - |
| contributor.author | Mittal, R | - |
| contributor.author | Patney, R K | - |
| date.accessioned | 2006-06-23T11:08:07Z | - |
| date.available | 2006-06-23T11:08:07Z | - |
| date.issued | 1989 | - |
| identifier.citation | Distributed Computing Systems, 524 - 531 | en |
| identifier.uri | http://eprint.iitd.ac.in/dspace/handle/2074/1688 | - |
| description.abstract | An augmented binary (AB) tree architecture is proposed with a view to providing fault tolerance. This architecture is an augmentation of an n-level full binary tree with n redundant nodes and 2 n+3n-6 redundant links. The AB tree can be configured into a full binary tree even when one node is faulty at each level. While functionally equivalent to the RAE-tree, the proposed AB tree has a regular topology, reduced number of maximum input-output channels per processor, and fewer wire crossovers when implemented using very large-scale integration layout. A reconfiguration algorithm, which constructs an n-level full binary tree from an n-level faulty AB tree, is given. A distributed fault diagnosis algorithm is given which runs concurrently on each nonfaulty processor, enabling each nonfaulty processor to identify all faulty processors | en |
| format.extent | 94119 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en |
| subject | augmented binary (AB) | en |
| subject | fault tolerance | en |
| subject | n-level full binary tree | en |
| subject | redundant nodes | en |
| subject | fewer wire crossovers | en |
| subject | diagnosis algorithm | en |
| title | Fault-tolerant analysis and algorithms for a proposed augmented binary tree architecture | en |
| type | Article | en |
| Appears in Collections: | Computer Science and Engineering
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Description |
Size | Format |
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| jainfau1989.pdf | | 91Kb | Adobe PDF | View/Open |
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