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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1700

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dc.contributor.authorShanbhag, Naresh R-
dc.contributor.authorNagchoudhuri, Dipankar-
dc.contributor.authorSiferd, Raymond E-
dc.contributor.authorVisweswaran, Gangiakond S-
dc.date.accessioned2006-06-26T04:05:11Z-
dc.date.available2006-06-26T04:05:11Z-
dc.date.issued1990-
dc.identifier.citationSolid-State Circuits, IEEE Journal of, 25(3), 790 - 799p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1700-
dc.description.abstractNovel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm2, is timed with a 2.2-MHz clock, and consumes 93 mW of poweren
dc.format.extent121320 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subject2-μm CMOS technologyen
dc.subjectbinary-to-quaternaryen
dc.subjectpseudo-NMOS circuitsen
dc.subjectquaternary sequential/storage logic array (QSLA)en
dc.titleQuaternary logic circuits in 2-μm CMOS technologyen
dc.typeArticleen
Appears in Collections:Electrical Engineering

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