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http://hdl.handle.net/2074/1700
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| Title: | Quaternary logic circuits in 2-μm CMOS technology |
| Authors: | Shanbhag, Naresh R
Nagchoudhuri, Dipankar
Siferd, Raymond E
Visweswaran, Gangiakond S |
| Keywords: | 2-μm CMOS technology
binary-to-quaternary
pseudo-NMOS circuits
quaternary sequential/storage logic array (QSLA) |
| Issue Date: | 1990 |
| Citation: | Solid-State Circuits, IEEE Journal of, 25(3), 790 - 799p. |
| Abstract: | Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm2, is timed with a 2.2-MHz clock, and consumes 93 mW of power |
| URI: | http://eprint.iitd.ac.in/dspace/handle/2074/1700 |
| Appears in Collections: | Electrical Engineering
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| shanbhagqua1990.pdf | | 118Kb | Adobe PDF | View/Open |
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