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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1704

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dc.contributor.authorPrasad, V C-
dc.contributor.authorPinjala, S N R-
dc.date.accessioned2006-06-26T04:15:53Z-
dc.date.available2006-06-26T04:15:53Z-
dc.date.issued1990-
dc.identifier.citationCircuits and Systems, 1, 37 - 40p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1704-
dc.description.abstractA method for the generation of a fault dictionary of a linear analog circuit is presented. The method is based on the well-known adjoined network concept. For an (n+1) node network and for an order of n2 faults, the method is of O(n 3) time complexity. A minimum of O(n4) is required, showing that the method is extremely fast. Using n processors, the method takes O(1) time on a single instruction multiple-data shared memory parallel computeren
dc.format.extent55219 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectlinear analog circuiten
dc.subjectadjoined network concepten
dc.subjectparallel computeren
dc.titleA fast algorithm for the generation of fault dictionary of linear analog circuits using adjoint network approachen
dc.typeArticleen
Appears in Collections:Electrical Engineering

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