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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1710

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dc.contributor.authorVisweswaran, G S-
dc.contributor.authorAli, Akhtar-uz-zaman M-
dc.contributor.authorLala, Parag K-
dc.contributor.authorHartmann, Carloss R P-
dc.identifier.citationSolid-State Circuits, IEEE Journal of, 26(6), 893 - 896p.en
dc.description.abstractA study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 μm there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open faulten
dc.format.extent49694 bytes-
dc.subjectpseudo-stuck-open faulten
dc.titleThe effects of transistor source-to-gate bridging faults in complex CMOS gatesen
Appears in Collections:Electrical Engineering

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