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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1716

Title: Signal delay in linear leaky RC mesh/tree
Authors: Jain, N K
Prasad, V C
Bhattacharyya, A B
Keywords: digital circuits
leaky RC tree/line/mesh
tree algorithm
Issue Date: 1991
Citation: VLSI Design, 195 - 199p.
Abstract: As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1716
Appears in Collections:Electrical Engineering

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