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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1729

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DC FieldValueLanguage
dc.contributor.authorNaseer, A R-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorA Kumar-
dc.date.accessioned2006-06-27T04:02:35Z-
dc.date.available2006-06-27T04:02:35Z-
dc.date.issued1994-
dc.identifier.citationVLSI Design, Proceedings of the Seventh International Conference on, 21 - 24p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1729-
dc.description.abstractPresents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or more closely connected RTL components and is realized using one or more CLBs. For this mapping onto CLBs, primarily function decomposition is employed. Conditions for some decompositions, disjunctive as well as nondisjunctive, useful in the FPGA context have been derived. As decomposition is a computation intensive process, some necessary conditions which are simple to check and eliminate a large percentage of trial partitions have been evolveden
dc.format.extent48172 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectmapping RTL structuresen
dc.titleFAST: FPGA targeted RTL structure synthesis techniqueen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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