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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1753
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Full metadata record
| DC Field | Value | Language |
|---|
| contributor.author | Chandra, V | - |
| contributor.author | Verma, M R | - |
| date.accessioned | 2006-06-27T06:17:57Z | - |
| date.available | 2006-06-27T06:17:57Z | - |
| date.issued | 1991 | - |
| identifier.citation | Design & Test of Computers, IEEE, 8(1), 58 - 66p. | en |
| identifier.uri | http://eprint.iitd.ac.in/dspace/handle/2074/1753 | - |
| description.abstract | A new approach to the design of microprocessor-based failsafe systems for railways that was used to design the FIRM architecture is described. The approach involves assigning appropriate levels of safety to system functions, depending on how critical they are, instead of using the same safety standard for all functions. The FIRM (short for failsafe interlocking system for railways using microprocessors) architecture uses a pair of processors that operate in a see-saw mode, with one or more pairs kept on standby. The installation and testing of an engineering prototype of the architecture that was fabricated for Indian Railways are discussed | en |
| format.extent | 116015 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en |
| subject | microprocessor-based failsafe | en |
| subject | FIRM architecture | en |
| title | A fail-safe interlocking system for railways | en |
| type | Article | en |
| Appears in Collections: | Electrical Engineering
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Files in This Item:
| File |
Description |
Size | Format |
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| chandrafai1991.pdf | | 113Kb | Adobe PDF | View/Open |
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