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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1766

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dc.contributor.authorNedungadi, P P-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorA Kumar-
dc.identifier.citationVLSI Design, 322 - 323p.en
dc.description.abstractThis paper presents an algorithm and its implementation for performing scheduling and operator allocation for data path synthesis. The main advantage of this approach is that it is capable of handling global time constraint as compered to earlier system [1] which expected the designer to artificially imposes a time constraint on the individual blocks. This is achieved by judiciously distributing the time available over various blocks to reduce the globle resource to requirements. Another feature of over approach is that it is capable of handling a library which may have operators with different speeds for the same operation . It is proposed to integrate this scheme in the IDEA system[2].en
dc.format.extent19773 bytes-
dc.subjectdata path synthesisen
dc.subjecthandling global timeen
dc.subjectglobal resourceen
dc.titleData path synthesis with global time constrainten
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