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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1874

Title: Efficient delay test generation for modular circuits
Authors: Ravikumar, C P
Agrawal, N
Agarwal, P
Keywords: module-level circuit
hierarchical circuits
Issue Date: 1996
Citation: VLSI, Proceedings, Sixth Great Lakes Symposium on, 220 - 225p.
Abstract: In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We propose a novel technique for path selection in module-level circuits and report efficient algorithms for delay test generation. MODET has been implemented and tested against a number of hierarchical circuits with impressive speedups in relation to gate level test generation
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1874
Appears in Collections:Electrical Engineering

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