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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1876
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| Title: | A novel BIST architecture with built-in self check |
| Authors: | Abdulla, M F
Ravikumar, C P
A Kumar |
| Keywords: | BIST architecture
pseudo-random test patterns |
| Issue Date: | 1996 |
| Citation: | VLSI Design, Proceedings, Ninth International Conference on, 57 - 60p. |
| Abstract: | We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The BILBO-based BIST architecture, used popularly in application-specific integrated circuits, suffers from two disadvantages. First, the initialization of the BILBO registers and the scanning out of the signatures are slow processes due to the sequential nature of these steps. Second, the test application time an a BILBO-based architecture does not depend on whether or not the circuit is faulty. It is typical to organize the testing procedure into one or more test sessions. In each test session, one or more functional modules are tested by applying pseudo-random test patterns. The responses of the functional modules are compressed into signatures which are captured into signature registers. Since the signature of the circuit is compared outside the chip, the test application must continue irrespective of whether or not a fault was detected in the middle of the t... |
| URI: | http://eprint.iitd.ac.in/dspace/handle/2074/1876 |
| Appears in Collections: | Electrical Engineering
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| abdullanov1996.pdf | | 49Kb | Adobe PDF | View/Open |
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