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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1876

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dc.contributor.authorAbdulla, M F-
dc.contributor.authorRavikumar, C P-
dc.contributor.authorA Kumar-
dc.identifier.citationVLSI Design, Proceedings, Ninth International Conference on, 57 - 60p.en
dc.description.abstractWe propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The BILBO-based BIST architecture, used popularly in application-specific integrated circuits, suffers from two disadvantages. First, the initialization of the BILBO registers and the scanning out of the signatures are slow processes due to the sequential nature of these steps. Second, the test application time an a BILBO-based architecture does not depend on whether or not the circuit is faulty. It is typical to organize the testing procedure into one or more test sessions. In each test session, one or more functional modules are tested by applying pseudo-random test patterns. The responses of the functional modules are compressed into signatures which are captured into signature registers. Since the signature of the circuit is compared outside the chip, the test application must continue irrespective of whether or not a fault was detected in the middle of the testing process. More seriously, aliasing errors may result when a single signature is used and testing continues in spite of one or more faulty responses. The test architecture proposed in this paper is abbe to improve the above situation by performing on-chip signature check. Thus, we allow testing and signature comparison to occur concurrently. We show that such a test method can give rise to significant reduction in test application timeen
dc.format.extent51045 bytes-
dc.subjectBIST architectureen
dc.subjectpseudo-random test patternsen
dc.titleA novel BIST architecture with built-in self checken
Appears in Collections:Electrical Engineering

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