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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1893
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| Title: | A scheme for multiple on-chip signature checking for embedded SRAMs |
| Authors: | Abdulla, M F
Ravikumar, C P
A Kumar |
| Keywords: | embedded memories
multiple on-chip signature checking |
| Issue Date: | 1997 |
| Citation: | European Design and Test Conference, ED&TC Proceedings, 625p. |
| Abstract: | Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results in significant reductions in aliasing probability at no significant increase in area in most cases, the test area and time overhead may be excessive if the circuit contains multiple embedded RAMs of various sizes. Example of such circuits are the ASICs for the telecommunications. In this paper, we propose a Static-RAM BIST scheme, based on the MOSC scheme, which is applicable for testing chips that have multiple embedded RAMs of various sizes |
| URI: | http://eprint.iitd.ac.in/dspace/handle/2074/1893 |
| Appears in Collections: | Computer Science and Engineering
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| abdullasch1997.pdf | | 14Kb | Adobe PDF | View/Open |
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