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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1893

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dc.contributor.authorAbdulla, M F-
dc.contributor.authorRavikumar, C P-
dc.contributor.authorA Kumar-
dc.date.accessioned2006-06-29T10:32:56Z-
dc.date.available2006-06-29T10:32:56Z-
dc.date.issued1997-
dc.identifier.citationEuropean Design and Test Conference, ED&TC Proceedings, 625p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1893-
dc.description.abstractPseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results in significant reductions in aliasing probability at no significant increase in area in most cases, the test area and time overhead may be excessive if the circuit contains multiple embedded RAMs of various sizes. Example of such circuits are the ASICs for the telecommunications. In this paper, we propose a Static-RAM BIST scheme, based on the MOSC scheme, which is applicable for testing chips that have multiple embedded RAMs of various sizesen
dc.format.extent15138 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectembedded memoriesen
dc.subjectmultiple on-chip signature checkingen
dc.titleA scheme for multiple on-chip signature checking for embedded SRAMsen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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