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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1895

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dc.contributor.authorNaseer, A R-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorA Kumar-
dc.identifier.citationVLSI Design, Proceedings, Tenth International Conference on, 134 - 139p.en
dc.description.abstractFor technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. A set of potentially optimal clock periods are chosen by evaluating `critical' paths to minimize the dead time associated with operations. Finally, the controller costs at these clock periods along with the execution times decide the optimal clock period. Extensive experimental results on data paths synthesized from high-level synthesis benchmarks establish both the utility as well as the efficiency of our approachen
dc.format.extent72094 bytes-
dc.subjectoptimal clock perioden
dc.subjectsynthesized RTL data pathen
dc.titleOptimal clock period for synthesized data pathsen
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