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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1897
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| DC Field | Value | Language |
| contributor.author | Aggarwal, G | - |
| contributor.author | Thaper, N | - |
| contributor.author | Aggarwal, K | - |
| contributor.author | Balakrishnan, M | - |
| contributor.author | S Kumar | - |
| date.accessioned | 2006-06-29T10:44:23Z | - |
| date.available | 2006-06-29T10:44:23Z | - |
| date.issued | 1997 | - |
| identifier.citation | VLSI Design, Proceedings, Tenth International Conference on, 370 - 375p. | en |
| identifier.uri | http://eprint.iitd.ac.in/dspace/handle/2074/1897 | - |
| description.abstract | Back-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, “hardwired” and cannot be used for a new function. In this paper, we discuss the design considerations and parameters of a general purpose reconfigurable co-processor. We also propose architecture of such a co-processor and discuss its implementation issues. The concept of a reconfigurable co-processor has become feasible because of the availability of static RAM based FPGAs. The key architectural features of our system are: scalable topology, shared memory space between the main processor and co-processor and efficient reconfigurability. A small prototype of the system has been implemented. We have demonstrated a two orders of speedup using our system over pure software solutions for a set of compute intensive applications | en |
| format.extent | 67629 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en |
| subject | reconfigurable co-processor | en |
| subject | scalable topology | en |
| title | A novel reconfigurable co-processor architecture | en |
| type | Article | en |
| Appears in Collections: | Computer Science and Engineering
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| File |
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Size | Format |
| aggarwalnov1997.pdf | | 66Kb | Adobe PDF | View/Open |
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