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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1897

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DC FieldValueLanguage
dc.contributor.authorAggarwal, G-
dc.contributor.authorThaper, N-
dc.contributor.authorAggarwal, K-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorS Kumar-
dc.date.accessioned2006-06-29T10:44:23Z-
dc.date.available2006-06-29T10:44:23Z-
dc.date.issued1997-
dc.identifier.citationVLSI Design, Proceedings, Tenth International Conference on, 370 - 375p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1897-
dc.description.abstractBack-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, “hardwired” and cannot be used for a new function. In this paper, we discuss the design considerations and parameters of a general purpose reconfigurable co-processor. We also propose architecture of such a co-processor and discuss its implementation issues. The concept of a reconfigurable co-processor has become feasible because of the availability of static RAM based FPGAs. The key architectural features of our system are: scalable topology, shared memory space between the main processor and co-processor and efficient reconfigurability. A small prototype of the system has been implemented. We have demonstrated a two orders of speedup using our system over pure software solutions for a set of compute intensive applicationsen
dc.format.extent67629 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectreconfigurable co-processoren
dc.subjectscalable topologyen
dc.titleA novel reconfigurable co-processor architectureen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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