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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1898

Title: Efficient implementation of multiple on-chip signature checking
Authors: Abdulla, M F
Ravikumar, C P
A Kumar
Keywords: detection latency
multiple on-chip signature comparison scheme
several benchmark circuits
Issue Date: 1997
Citation: VLSI Design, Proceedings., Tenth International Conference on, 297 - 302p.
Abstract: Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection latency since it is not until the signatures are scanned out and compared off-chip that a fault become apparent. Aliasing, which is a fallout of long detection latency, is a serious problem. We have proposed an improved BIST architecture which supports on-chip comparison of multiple signatures to minimize the probability of aliasing and total test time. Also we quantified the aliasing probability of the “Multiple On-chip Signature Comparison scheme” (MOSC) scheme proposed. In this paper, we describe an efficient implementation of the MOSC test architecture and report results on several benchmark circuits. We describe different optimization methods to reduce the overall test control area
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1898
Appears in Collections:Computer Science and Engineering

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