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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1900

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DC FieldValueLanguage
dc.contributor.authorHarikumer, S-
dc.contributor.authorS Kumar-
dc.date.accessioned2006-06-29T10:46:26Z-
dc.date.available2006-06-29T10:46:26Z-
dc.date.issued1997-
dc.identifier.citationVLSI Design, Proceedings, Tenth International Conference on, 239 - 242p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1900-
dc.description.abstractSpeeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems (RS) built using FPGA's offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purposeen
dc.format.extent49506 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectreconfigurable systemsen
dc.subjectapproximate algorithmsen
dc.titleMultiobjective search based algorithms for circuit partitioning problem for acceleration of logic simulationen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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