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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1918

Title: Digital pulse logic-a new paradigm for the hardware realization of combinational and sequential digital logic
Authors: Chaudhary, A
Jayadeva
Dutta Roy, S C
Keywords: pulse stream neural network
digital pulse logic
wide noise margins
Issue Date: 1998
Citation: TENCON IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control, 1, 124 - 127p.
Abstract: We describe a pulse stream neural network approach for realising combinational and sequential logical functions, referred to as digital pulse logic. The elemental unit or neuron is based on a modified phase locked loop, which we use to design digital gates and sequential blocks. Such implementations offer very wide noise margins and are thus more robust in comparison with conventional implementations. We discuss both open loop and closed loop implementations
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1918
Appears in Collections:Electrical Engineering

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