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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1941

Title: Improving area efficiency of FIR filters implemented using distributed arithmetic
Authors: Sinha, A
Mehendale, M
Keywords: distributed arithmetic
heuristic approach
Issue Date: 1998
Citation: VLSI Design, Proceedings, Eleventh International Conference on, 104 - 109p.
Abstract: In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1941
Appears in Collections:Electrical Engineering

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