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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1943

Title: A low power 256 KB SRAM design
Authors: Bhaumik, B
Pradhan, P
Visweswaran, G S
Varambally, R
Hardi, A
Keywords: divided word line
reduce power consumption
Issue Date: 1998
Citation: VLSI Design, Proceedings Twelfth International Conference On, 67 - 70p.
Abstract: In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGS Thomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably. Simulation results confirmed the effectiveness of our approach
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1943
Appears in Collections:Electrical Engineering

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