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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1943
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Full metadata record
| DC Field | Value | Language |
|---|
| contributor.author | Bhaumik, B | - |
| contributor.author | Pradhan, P | - |
| contributor.author | Visweswaran, G S | - |
| contributor.author | Varambally, R | - |
| contributor.author | Hardi, A | - |
| date.accessioned | 2006-07-03T05:35:01Z | - |
| date.available | 2006-07-03T05:35:01Z | - |
| date.issued | 1998 | - |
| identifier.citation | VLSI Design, Proceedings Twelfth International Conference On, 67 - 70p. | en |
| identifier.uri | http://eprint.iitd.ac.in/dspace/handle/2074/1943 | - |
| description.abstract | In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGS Thomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably. Simulation results confirmed the effectiveness of our approach | en |
| format.extent | 56107 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en |
| subject | divided word line | en |
| subject | reduce power consumption | en |
| title | A low power 256 KB SRAM design | en |
| type | Article | en |
| Appears in Collections: | Electrical Engineering
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Files in This Item:
| File |
Description |
Size | Format |
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| bhaumiklow1999.pdf | | 54Kb | Adobe PDF | View/Open |
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