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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1943

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dc.contributor.authorBhaumik, B-
dc.contributor.authorPradhan, P-
dc.contributor.authorVisweswaran, G S-
dc.contributor.authorVarambally, R-
dc.contributor.authorHardi, A-
dc.identifier.citationVLSI Design, Proceedings Twelfth International Conference On, 67 - 70p.en
dc.description.abstractIn this paper a low power SRAM design is presented. Existing SRAM architectures used in SGS Thomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably. Simulation results confirmed the effectiveness of our approachen
dc.format.extent56107 bytes-
dc.subjectdivided word lineen
dc.subjectreduce power consumptionen
dc.titleA low power 256 KB SRAM designen
Appears in Collections:Electrical Engineering

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