DSpace
 

EPrints@IIT Delhi >
Faculty Research Publicatons  >
Electrical Engineering >

Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1945

Title: Hybrid testing schemes based on mutual and signature testing
Authors: Abdulla, M F
Ravikumar, C P
A Kumar
Keywords: built-in self-test
mutual checking
aliasing
self loops
Issue Date: 1998
Citation: VLSI Design, Proceedings, Eleventh International Conference on, 293 - 296p.
Abstract: Signature based techniques have been well known for the built-in self-test of integrated systems. We propose a novel test architecture which uses a judicious combination of mutual testing and signature testing to achieve low test area overhead, low aliasing probability and low test application time. The proposed architecture is powerful for testing highly concurrent systems in applications such as iterative logic arrays, real-time systems, systolic arrays, and low-latency pipelines which tend to have a large number of functional modules of a similar nature. We provide graph-theoretic optimization algorithms to optimize the test area and test application time of the resulting test architecture
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1945
Appears in Collections:Electrical Engineering

Files in This Item:

File Description SizeFormat
abdullahyb1998.pdf54.55 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback