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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1945

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dc.contributor.authorAbdulla, M F-
dc.contributor.authorRavikumar, C P-
dc.contributor.authorA Kumar-
dc.identifier.citationVLSI Design, Proceedings, Eleventh International Conference on, 293 - 296p.en
dc.description.abstractSignature based techniques have been well known for the built-in self-test of integrated systems. We propose a novel test architecture which uses a judicious combination of mutual testing and signature testing to achieve low test area overhead, low aliasing probability and low test application time. The proposed architecture is powerful for testing highly concurrent systems in applications such as iterative logic arrays, real-time systems, systolic arrays, and low-latency pipelines which tend to have a large number of functional modules of a similar nature. We provide graph-theoretic optimization algorithms to optimize the test area and test application time of the resulting test architectureen
dc.format.extent55858 bytes-
dc.subjectbuilt-in self-testen
dc.subjectmutual checkingen
dc.subjectself loopsen
dc.titleHybrid testing schemes based on mutual and signature testingen
Appears in Collections:Electrical Engineering

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