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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1950

Title: Synthesis of testable RTL designs
Authors: Ravikumar, C P
Gupta, S
Jajoo, A
Keywords: synthesis of testable RTL designs
application-specific integrated circuits
Issue Date: 1998
Citation: VLSI Design, Proceedings, Eleventh International Conference on, 187 - 192p.
Abstract: With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to “learn” to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time
URI: http://eprint.iitd.ac.in/dspace/handle/2074/1950
Appears in Collections:Electrical Engineering

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