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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1969

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dc.contributor.authorRavikumar, C P-
dc.contributor.authorMittal, A-
dc.date.accessioned2006-07-03T09:24:29Z-
dc.date.available2006-07-03T09:24:29Z-
dc.date.issued1999-
dc.identifier.citationVLSI Design, Proceedings Twelfth International Conference On, 635 - 639p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1969-
dc.description.abstractIncreasingly, VLSI systems are being designed using macro blocks and predesigned cores. Since the clock rate at which these circuits operate is steadily increasing, it is important to perform delay testing on modern VLSI chips and systems. Algorithms for delay test generation and delay fault simulation are known to be compute-intensive. Many of these algorithms require gate-level descriptions of circuits which are difficult to generate and may be even impossible to provide when the designer has made use of predesigned cores. Hierarchical testing appears to be an attractive alternative in such cases. Tests generated for logic blocks may be reused to generate tests for larger systems comprising of the logic blocks, hence reducing the total effort in test generation. Tests show in this paper that the computational effort spent in fault simulation can also be reduced using a hierarchical approach. The simulator HIDEFS described in this paper exploits the modular nature of the circuit to save on the memory requirement as well as execution time requirement of fault simulationen
dc.format.extent58575 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectgate-level descriptionsen
dc.subjecthierarchicalen
dc.titleHierarchical delay fault simulationen
dc.typeArticleen
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