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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1970

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dc.contributor.authorBhaumik, B-
dc.contributor.authorVisweswaran, G S-
dc.contributor.authorLakshminarasimhan, R-
dc.date.accessioned2006-07-03T09:25:19Z-
dc.date.available2006-07-03T09:25:19Z-
dc.date.issued1999-
dc.identifier.citationVLSI Design, Proceedings Twelfth International Conference On, 95 - 98p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1970-
dc.description.abstractGeneralized Modified Positional Syndrome (GMPS), of order p, a new compaction scheme for test output data is presented. The order p determines the aliasing probability and the amount of hardware overhead required to implement the scheme. GMPS of order two gives an aliasing probability about an order of magnitude lower than the best scheme reported in literature with minimal extra hardware. A hardware realization scheme for GMPS has been presented. The scheme uses adders with feedbacken
dc.format.extent42309 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectgeneralized modified positional syndromeen
dc.titleA new test compression schemeen
dc.typeArticleen
Appears in Collections:Electrical Engineering

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