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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1985

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dc.contributor.authorShrivastava, A-
dc.contributor.authorH Kumar-
dc.contributor.authorKapoor, S-
dc.contributor.authorS Kumar-
dc.contributor.authorBalakrishnan, M-
dc.date.accessioned2006-07-03T09:42:15Z-
dc.date.available2006-07-03T09:42:15Z-
dc.date.issued2000-
dc.identifier.citationVLSI Design, Thirteenth International Conference on, 110 - 113p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1985-
dc.description.abstractAn important aspect of hardware-software co-design is partitioning of tasks to be scheduled on the hardware and software resources. Existing approaches separate partitioning and scheduling in two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approaches may lead to sub-optimal results. In this paper, we present an integrated hardware/software scheduling, partitioning and binding strategy. We use dynamic programming techiques to devise an optimal solution for partitioning of a given concurrent task graph which models the co-design problem, for execution on one software (single CPU) and several hardware resources (multiple FPGAs), with the objective of minimizing the total execution time. Our implementation shows that we can solve problem instances where the task graph has 40 nodes and 600 edges in less than a seconden
dc.format.extent42841 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectvice versaen
dc.subjectconcurrent task graphen
dc.titleOptimal hardware/software partitioning for concurrent specification using dynamic programmingen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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