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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/1987

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dc.contributor.authorPrasad, V C-
dc.contributor.authorBabu, N S C-
dc.date.accessioned2006-07-03T09:43:31Z-
dc.date.available2006-07-03T09:43:31Z-
dc.date.issued2000-
dc.identifier.citationInstrumentation and Measurement, IEEE Transactions on, 49(6), 1289 - 1297p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/1987-
dc.description.abstractIn this paper, the selection of test nodes has been studied extensively and efficient techniques are proposed. Two broad categories of methods called inclusion methods and exclusion methods are suggested. Strategies are presented to select or delete a test node without affecting the diagnosis capabilities. Examples show that these strategies give a lesser number of test nodes some times. Starting from the fault-wise integer coded table of the test circuit, sorting is employed to generate valid sets and minimal sets. The order of computation of these methods is shown to depend linearly on number of test nodes. It is also proportional to (f log f) where “f” is the number of faults. This is much faster than well-known methods. The concept of minimal set of test nodes is new in analog circuit fault diagnosis. Polynomial time algorithms are proposed in this paper for the first time to generate such setsen
dc.format.extent148408 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectfault-wise integer codeden
dc.subjectanalog circuit fault diagnosisen
dc.titleSelection of test nodes for analog fault diagnosis in dictionary approachen
dc.typeArticleen
Appears in Collections:Electrical Engineering

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