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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1993
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| Title: | Testing interconnects in a system chip |
| Authors: | Ravikumar, C P
Chopra, S |
| Keywords: | system-on-chip
chip-level interconnects
graph-theoretic framework |
| Issue Date: | 2000 |
| Citation: | VLSI Design, Thirteenth International Conference on, 388 - 391p. |
| Abstract: | Testing of interconnects on a printed circuit board has been studied and the procedure has been standardized in the IEEE 1149.1 (JTAG) standard. The system-on-chip (SOC) technology allows us to integrate on the same chip, most of the electronics on a PCB. However, since an SOC operates at a much higher speed and has a very large packaging density, testing its interconnects is different. For example, one must address the crosstalk faults with chip-level interconnects. Not much literature exists on the topic of testing interconnects in core-based systems. We propose a graph-theoretic framework for the problem and a genetic algorithm for testing core interconnects. Our algorithm addresses the issues of test application time, test area overhead, fault-coverage and test power |
| URI: | http://eprint.iitd.ac.in/dspace/handle/2074/1993 |
| Appears in Collections: | Electrical Engineering
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| ravikumartes2000.pdf | | 75Kb | Adobe PDF | View/Open |
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