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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/1993
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Full metadata record
| DC Field | Value | Language |
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| contributor.author | Ravikumar, C P | - |
| contributor.author | Chopra, S | - |
| date.accessioned | 2006-07-10T04:19:56Z | - |
| date.available | 2006-07-10T04:19:56Z | - |
| date.issued | 2000 | - |
| identifier.citation | VLSI Design, Thirteenth International Conference on, 388 - 391p. | en |
| identifier.uri | http://eprint.iitd.ac.in/dspace/handle/2074/1993 | - |
| description.abstract | Testing of interconnects on a printed circuit board has been studied and the procedure has been standardized in the IEEE 1149.1 (JTAG) standard. The system-on-chip (SOC) technology allows us to integrate on the same chip, most of the electronics on a PCB. However, since an SOC operates at a much higher speed and has a very large packaging density, testing its interconnects is different. For example, one must address the crosstalk faults with chip-level interconnects. Not much literature exists on the topic of testing interconnects in core-based systems. We propose a graph-theoretic framework for the problem and a genetic algorithm for testing core interconnects. Our algorithm addresses the issues of test application time, test area overhead, fault-coverage and test power | en |
| format.extent | 76937 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en |
| subject | system-on-chip | en |
| subject | chip-level interconnects | en |
| subject | graph-theoretic framework | en |
| title | Testing interconnects in a system chip | en |
| type | Article | en |
| Appears in Collections: | Electrical Engineering
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Files in This Item:
| File |
Description |
Size | Format |
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| ravikumartes2000.pdf | | 75Kb | Adobe PDF | View/Open |
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