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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2033

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DC FieldValueLanguage
dc.contributor.authorJain, S C-
dc.contributor.authorA Kumar-
dc.contributor.authorS Kumar-
dc.date.accessioned2006-08-04T03:55:50Z-
dc.date.available2006-08-04T03:55:50Z-
dc.date.issued2002-
dc.identifier.citationRapid System Prototyping, Proceedings 13th IEEE International Workshop on, 66 - 73p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/2033-
dc.description.abstractMulti-FPGA Boards (MFBs) have been in use for more than a decade for emulation of the digital circuits in many applications. Key feature of an MFB architecture is its inter-FPGA connections. There are two types of inter-FPGA connections namely: i) fixed connection (FC)-connecting a pair of FPGAs through a dedicated wire between them, ii) programmable connection (PC)-connecting a pair of FPGAs through a programmable switch like Field-Programmable Interconnect Device (FPID). Hence, a PC requires two wires compared to one wire in FC. Khalid et al. (1999) have shown that the MFBs consisting of both the types of connections (hybrid MFBs) are better than other architectures for emulation of the circuits, if the number of PCs are minimum required. Hence, we evaluate the hybrid MFBs for the required number of PCs as an evaluation metric. Availability of technology mapping, partitioning, embedding and routing tools is another important requirement for emulation. A routing tool (multi-hop router) prefers one or more unused FCs (multi-hops) in lieu of one PC. Available multihop routers are specific to MFB architecture and use unlimited hops in the routes. For evaluation, a generic multi-hop router for any hybrid architecture is required which obeys the given limit on maximum number of hops in every route. This paper presents the development of routing tool for the same. A heuristic, a lower bound and an optimal algorithm has been implemented for this purpose. For the test cases, it has been observed that the optimal results (within 3 hours) are achievable by the heuristic (within a minute). Also the results are more precise than the available results.en
dc.format.extent123404 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectmulti-FPGA boardsen
dc.subjectfield-programmable interconnect deviceen
dc.subjectmulti-hop routeren
dc.titleHybrid Multi-FPGA board evaluation by limiting multi-hop routingen
dc.typeArticleen
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