DSpace
 

EPrints@IIT Delhi >
Faculty Research Publicatons  >
Computer Science and Engineering >

Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2052

Title: Evaluating register file size in ASIP design
Authors: Jain, Manoj Kumar
Wehmeyer, Lars
Steinke, Stefan
Marwedel, Peter
Balakrishnan, M
Keywords: register file
synthesis
instruction set
instruction power model
register spill
application specific instruction set processor
Issue Date: 2001
Citation: Hardware/Software Codesign, CODES Proceedings of the Ninth International Symposium on, 109 - 114p.
Abstract: Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performance
URI: http://eprint.iitd.ac.in/dspace/handle/2074/2052
Appears in Collections:Computer Science and Engineering

Files in This Item:

File Description SizeFormat
jaineva2001.pdf118.49 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback