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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2052

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dc.contributor.authorJain, Manoj Kumar-
dc.contributor.authorWehmeyer, Lars-
dc.contributor.authorSteinke, Stefan-
dc.contributor.authorMarwedel, Peter-
dc.contributor.authorBalakrishnan, M-
dc.date.accessioned2006-08-07T03:32:38Z-
dc.date.available2006-08-07T03:32:38Z-
dc.date.issued2001-
dc.identifier.citationHardware/Software Codesign, CODES Proceedings of the Ninth International Symposium on, 109 - 114p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/2052-
dc.description.abstractInterest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performanceen
dc.format.extent121337 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectregister fileen
dc.subjectsynthesisen
dc.subjectinstruction seten
dc.subjectinstruction power modelen
dc.subjectregister spillen
dc.subjectapplication specific instruction set processoren
dc.titleEvaluating register file size in ASIP designen
dc.typeArticleen
Appears in Collections:Computer Science and Engineering

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