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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2094

Title: Exploring storage organization in ASIP synthesis
Authors: Jain, M K
Balakrishnan, M
A Kumar
Keywords: ASIP synthesis
storage exploration
scheduler based technique
register file
register windowes
cache configurations
Issue Date: 2003
Citation: Digital System Design, Proceedings Euromicro Symposium on, 120 - 127p.
Abstract: Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster. However, existing scheduler based approaches do not help in exploring storage organization. We present a scheduler based technique for exploring register file size, number of register windows and cache configurations in an integrated manner. Performances for different register file sizes are estimated by predicting the number of memory spills and its delay. The technique employed does not require explicit register assignment. The number of context switches leading to spills is estimated for evaluating the time penalty due to a limited number of register windows and cache simulator is used for estimating cache performance. The proposed technique has been validated for several benchmarks over a range of processors by comparing our estimates to the results obtained from standard simulation tools. The processors include ARM7TDMI, LEON and Trimedia (TM-1000).
URI: http://eprint.iitd.ac.in/dspace/handle/2074/2094
Appears in Collections:Computer Science and Engineering

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