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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2094

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dc.contributor.authorJain, M K-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorA Kumar-
dc.identifier.citationDigital System Design, Proceedings Euromicro Symposium on, 120 - 127p.en
dc.description.abstractPerformance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster. However, existing scheduler based approaches do not help in exploring storage organization. We present a scheduler based technique for exploring register file size, number of register windows and cache configurations in an integrated manner. Performances for different register file sizes are estimated by predicting the number of memory spills and its delay. The technique employed does not require explicit register assignment. The number of context switches leading to spills is estimated for evaluating the time penalty due to a limited number of register windows and cache simulator is used for estimating cache performance. The proposed technique has been validated for several benchmarks over a range of processors by comparing our estimates to the results obtained from standard simulation tools. The processors include ARM7TDMI, LEON and Trimedia (TM-1000).en
dc.format.extent585001 bytes-
dc.subjectASIP synthesisen
dc.subjectstorage explorationen
dc.subjectscheduler based techniqueen
dc.subjectregister fileen
dc.subjectregister windowesen
dc.subjectcache configurationsen
dc.titleExploring storage organization in ASIP synthesisen
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