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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2231

Title: Speeding up program execution using reconfigurable hardware and a hardware function library
Authors: Jain, S
Balakrishnan, M
A Kumar
Kumar, S
Keywords: uniprocessor host
pre-synthesized
heuristic
Issue Date: 1998
Citation: VLSI Design, Proceedings, Eleventh International Conference on, 400 - 405p.
Abstract: This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a uniprocessor host and a board with dynamically reconfigurable FPGAs and memory modules; second, a library of functions pre-synthesized for hardware or software implementation; and third, a tool which takes as input an application described in C and partitions it into hardware and software parts at functional granularity using information obtained by profiling the application. An important feature of the partitioning tool is a new efficient heuristic specifically suited for the architecture with reconfigurable hardware
URI: http://eprint.iitd.ac.in/dspace/handle/2074/2231
Appears in Collections:Computer Science and Engineering

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