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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2231

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dc.contributor.authorJain, S-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorA Kumar-
dc.contributor.authorKumar, S-
dc.identifier.citationVLSI Design, Proceedings, Eleventh International Conference on, 400 - 405p.en
dc.description.abstractThis paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a uniprocessor host and a board with dynamically reconfigurable FPGAs and memory modules; second, a library of functions pre-synthesized for hardware or software implementation; and third, a tool which takes as input an application described in C and partitions it into hardware and software parts at functional granularity using information obtained by profiling the application. An important feature of the partitioning tool is a new efficient heuristic specifically suited for the architecture with reconfigurable hardwareen
dc.format.extent2794686 bytes-
dc.subjectuniprocessor hosten
dc.titleSpeeding up program execution using reconfigurable hardware and a hardware function libraryen
Appears in Collections:Computer Science and Engineering

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