EPrints@IIT Delhi >
Faculty Research Publicatons  >
Electrical Engineering >

Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2238

Title: Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET
Authors: Kumar, M Jagdesh
Verma, Vikram
Keywords: SiGe source
floating body
SOI structure
VLSI applications
Issue Date: 2002
Citation: Reliability, IEEE Transactions on, 5(1), 367 - 370p.
Abstract: For the first time, we report the combined application of a SiGe source and a delta-doped p+ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications
URI: http://eprint.iitd.ac.in/dspace/handle/2074/2238
Appears in Collections:Electrical Engineering

Files in This Item:

File Description SizeFormat
kumareli2002.pdf297.31 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.


Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback