|
EPrints@IIT Delhi >
Faculty Research Publicatons >
Electrical Engineering >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/2074/2268
|
| Title: | Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI for VLSI applications |
| Authors: | M Jagadesh Kumar
Rao, D V |
| Keywords: | schottky collector bipolar transistor
silicon-on-insulator
Si lateral NPN BJT
SiC emitter lateral NPN HBT
BiCMOS technology |
| Issue Date: | 2004 |
| Citation: | Circuits, Devices and Systems, IEE Proceedings, 151(1), 63 - 67p. |
| Abstract: | A novel bipolar transistor structure, namely, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI) substrate is explored using two-dimensional (2-D) simulation. A comprehensive comparison of the proposed structure with its equivalent Si lateral NPN BJT and an SiC emitter lateral NPN HBT is presented. Based on simulation results, the authors demonstrate for the first time that the proposed SiC emitter lateral NPM transistor shows superior performance in terms of high current gain and cut-off frequency, reduced collector resistance, negligible reverse recovery time and suppressed Kirk effect over its equivalent Si lateral NPN BJT and SiC emitter lateral NPN HBT. A simple fabrication process compatible with BiCMOS technology is also discussed. |
| URI: | http://eprint.iitd.ac.in/dspace/handle/2074/2268 |
| Appears in Collections: | Electrical Engineering
|
Files in This Item:
| File |
Description |
Size | Format |
|---|
| kumarpro2004.pdf | | 1269Kb | Adobe PDF | View/Open |
|
Show full item record
All items in DSpace are protected by copyright, with all rights reserved.
|
