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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2268

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dc.contributor.authorM Jagadesh Kumar-
dc.contributor.authorRao, D V-
dc.date.accessioned2006-11-20T06:10:13Z-
dc.date.available2006-11-20T06:10:13Z-
dc.date.issued2004-
dc.identifier.citationCircuits, Devices and Systems, IEE Proceedings, 151(1), 63 - 67p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/2268-
dc.description.abstractA novel bipolar transistor structure, namely, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI) substrate is explored using two-dimensional (2-D) simulation. A comprehensive comparison of the proposed structure with its equivalent Si lateral NPN BJT and an SiC emitter lateral NPN HBT is presented. Based on simulation results, the authors demonstrate for the first time that the proposed SiC emitter lateral NPM transistor shows superior performance in terms of high current gain and cut-off frequency, reduced collector resistance, negligible reverse recovery time and suppressed Kirk effect over its equivalent Si lateral NPN BJT and SiC emitter lateral NPN HBT. A simple fabrication process compatible with BiCMOS technology is also discussed.en
dc.format.extent1300055 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectschottky collector bipolar transistoren
dc.subjectsilicon-on-insulatoren
dc.subjectSi lateral NPN BJTen
dc.subjectSiC emitter lateral NPN HBTen
dc.subjectBiCMOS technologyen
dc.titleProposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI for VLSI applicationsen
dc.typeArticleen
Appears in Collections:Electrical Engineering

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