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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2294

Title: Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review
Authors: Chaudhry, Anurag
M Jagadesh Kumar
Keywords: MOS device
silicon-on-insulator (SOI)
short-channel effects
ULSI applications
dual-material gate
drain-induced barrier lowering
ultra-small geometry
Issue Date: 2004
Citation: Device and Materials Reliability, IEEE Transactions on, 4(1), 99 - 109p.
Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.
URI: http://eprint.iitd.ac.in/dspace/handle/2074/2294
Appears in Collections:Electrical Engineering

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