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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/2351

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dc.contributor.authorM Jagadesh Kumar-
dc.contributor.authorChaudhry, Anurag-
dc.date.accessioned2006-12-08T03:20:01Z-
dc.date.available2006-12-08T03:20:01Z-
dc.date.issued2004-
dc.identifier.citationElectron Devices, IEEE Transactions on, 51(4), 569 - 574p.en
dc.identifier.urihttp://eprint.iitd.ac.in/dspace/handle/2074/2351-
dc.description.abstractA two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.en
dc.format.extent497048 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectsilicon-on-insulatoren
dc.subjectMOSFETsen
dc.subjectshort-channel effects (SCEs)en
dc.subjectdrain-induced barrier-loweringen
dc.subjectsubmicrometer regimeen
dc.subject2-D numerical simulationsen
dc.titleTwo-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEsen
dc.typeArticleen
Appears in Collections:Electrical Engineering

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