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Please use this identifier to cite or link to this item: http://eprint.iitd.ac.in/handle/2074/783

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dc.contributor.authorAbdulla, M F-
dc.contributor.authorRavikumar, C P-
dc.contributor.authorKumar, Anshul-
dc.identifier.citationJournal of Systems Architecture, 46(2), 181-199en
dc.description.abstractEmbedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an embedded memory poses a challenge to a system test engineer, due to its limited controllability and observability. In this paper, we propose a pseudorandom built-in self test (BIST) scheme to solve this problem. Our technique is based on a test architecture known as multiple on-line signature checking (MOSC) which overs a very low aliasing probability and a high degree of confidence in testing. While the MOSC scheme is suficiently general and applicable to any digital circuit, it can especially be optimized for circuits with embedded memories. We present interesting test scheduling algorithms that reduce the overhead of testing. On several industry-standard benchmark circuits, we report up to 35% savings in test area overhead.en
dc.format.extent807031 bytes-
dc.subjectEmbedded memoriesen
dc.subjectBuilt-in self testen
dc.subjectMultiple signature comparisonen
dc.titleA scheme for multiple on-chip signature checking for embedded SRAMSen
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