Showing 20 items.
| Date of Issue | Title |
Authors |
|---|
| 1990 | SYMCAD: synthesis of microprogrammed control for automated VLSI design | Priyadarshan, B L; Balakrishnan, M; A Kumar; Visweswaran, G S |
| 1992 | Data path synthesis with global time constraint | Nedungadi, P P; Balakrishnan, M; A Kumar |
| 1994 | FAST: FPGA targeted RTL structure synthesis technique | Naseer, A R; Balakrishnan, M; A Kumar |
| 1996 | Protein fractionationin a vortex flow filter. II: Separation of simulated mixtures | Balakrishnan, M; Agarwal, G P |
| 1996 | Protein fractionation in a vortex flow filter. I: Effect of systemhydrodynamics and solution environment on single protein transmission | Balakrishnan, M; Agarwal, G P |
| 1997 | A novel reconfigurable co-processor architecture | Aggarwal, G; Thaper, N; Aggarwal, K; Balakrishnan, M; S Kumar |
| 1997 | Optimal clock period for synthesized data paths | Naseer, A R; Balakrishnan, M; A Kumar |
| 1998 | Speeding up program execution using reconfigurable hardware and a hardware function library | Jain, S; Balakrishnan, M; A Kumar; Kumar, S |
| 2000 | Optimal hardware/software partitioning for concurrent specification using dynamic programming | Shrivastava, A; H Kumar; Kapoor, S; S Kumar; Balakrishnan, M |
| 2000 | A specialized graduate program in VLSI design: a success story | Balakrishnan, M |
| 2000 | Interface synthesis: issues and approaches | Rajawat, A; Balakrishnan, M; A Kumar |
| 2001 | ASIP design methodologies: survey and issues | Jain, M K; Balakrishnan, M; A Kumar |
| 2001 | Evaluating register file size in ASIP design | Jain, Manoj Kumar; Wehmeyer, Lars; Steinke, Stefan; Marwedel, Peter; Balakrishnan, M |
| 2002 | A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units | Middha, Bhuvan; Raj, Varun; Gangwar, Anup; Kumar, Anshul; Balakrishnan, M; Ienne, Paolo |
| 2002 | A new performance evaluation approach for system level design space exploration | Joshi, C P; A Kumar; Balakrishnan, M |
| 2002 | A new divide and conquer method for achieving high speed division in hardware | Mohan, M; Rohini, K; A Kumar; Balakrishnan, M |
| 2003 | Exploring register file and memory organization in ASIP synthesis | Balakrishnan, M; Kumar, Anshul; Jain, Manoj Kumar |
| 2003 | SoC synthesis with automatic hardware-software interface generation | Singh, A; Chhabra, A; Gangwar, A; Dwivedi, B K; Balakrishnan, M; A Kumar |
| 2003 | Exploring storage organization in ASIP synthesis | Jain, M K; Balakrishnan, M; A Kumar |
| 2004 | Synthesis of application specific multiprocessor architectures for process networks | Dwivedi, Basant Kumar; Anshul Kumar; Balakrishnan, M |
