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Optimal clock period for synthesized data paths

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Author: Naseer, A R; Balakrishnan, M; A Kumar

Advisor: Advisor

Date: 1997

Publisher:
Citation: VLSI Desig

Series/Report no.:
Item Type: Article

Keywords: optimal clock period; synthesized RTL data path

Abstract: For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. A set of potentially optimal clock periods are chosen by evaluating `critical' paths to minimize the dead time associated with operations. Finally, the controller costs at these clock periods along with the execution times decide the optimal clock period. Extensive experimental results on data paths synthesized from high-level synthesis benchmarks establish both the utility as well as the efficiency of our approach
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Shankar B. Chavan
Computer Applications Division
Central Library, IIT Delhi
shankar.chavan@library.iitd.ac.in
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etd@IISc
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Shankar B. Chavan
Computer Applications Division
Central Library, IIT Delhi
shankar.chavan@library.iitd.ac.in
NDLTD
Shodhganga
NDL
ePrints@IISc
etd@IISc
IR@IIT Bombay
NewsClips @IITD
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  • youtube
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