Author: | Jain, S; Balakrishnan, M; A Kumar; Kumar, S |
Advisor: | Advisor |
Date: | 1998
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Publisher: | |
Citation: | VLSI Desig
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Series/Report no.: |
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Item Type: | Article
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Keywords: | uniprocessor host; pre-synthesized; heuristic |
Abstract: | This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a uniprocessor host and a board with dynamically reconfigurable FPGAs and memory modules; second, a library of functions pre-synthesized for hardware or software implementation; and third, a tool which takes as input an application described in C and partitions it into hardware and software parts at functional granularity using information obtained by profiling the application. An important feature of the partitioning tool is a new efficient heuristic specifically suited for the architecture with reconfigurable hardware |