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dc.contributor.authorJain, S
dc.contributor.authorBalakrishnan, M
dc.contributor.authorA Kumar
dc.contributor.authorKumar, S
dc.date.accessioned2006-10-12T04:19:36Z
dc.date.accessioned2019-02-09T07:28:14Z
dc.date.available2006-10-12T04:19:36Z
dc.date.available2019-02-09T07:28:14Z
dc.date.issued1998
dc.identifier.citationVLSI Design, Proceedings, Eleventh International Conference on, 400 - 405p.en
dc.identifier.urihttp://localhost:8080/xmlui/handle/12345678/2231
dc.description.abstractThis paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a uniprocessor host and a board with dynamically reconfigurable FPGAs and memory modules; second, a library of functions pre-synthesized for hardware or software implementation; and third, a tool which takes as input an application described in C and partitions it into hardware and software parts at functional granularity using information obtained by profiling the application. An important feature of the partitioning tool is a new efficient heuristic specifically suited for the architecture with reconfigurable hardwareen
dc.format.extent2794686 bytes
dc.format.mimetypeapplication/msword
dc.language.isoenen
dc.subjectuniprocessor hosten
dc.subjectpre-synthesizeden
dc.subjectheuristicen
dc.titleSpeeding up program execution using reconfigurable hardware and a hardware function libraryen
dc.typeArticleen


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